1. Field of the Invention
The present invention relates to a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method, and more particularly, to a layout method of a power line for a semiconductor integrated circuit where a power line and a decoupling capacitor constituting the semiconductor integrated circuit are arranged in the same region, and a semiconductor integrated circuit manufactured by the layout method.
2. Discussion of Related Art
In general, various researches on layout methods for power lines and semiconductor devices are done in a semiconductor integrated circuit. Hereinafter, the layout of a conventional semiconductor integrated circuit will be described with reference to the accompanying drawings.
FIG. 1 illustrates a power line layout of a conventional semiconductor integrated circuit including a power line and a decoupling capacitor (refer to Korean Patent Publication No. 2002-0077040 entitled “semiconductor integrated circuit and layout design method of power line”), and FIG. 2 illustrates a power line layout of another conventional semiconductor integrated circuit including a power line and a decoupling capacitor (refer to U.S. Patent Publication No. 2005/0071798 entitled “Power supply layout for an integrated circuit”).
Referring to FIG. 1, power lines 101 and 102 (VDD and GND) surround a core 103 of a semiconductor integrated circuit 100, and a decoupling capacitor 104 for reducing noises of the power lines 101 and 102 is arranged within the core 103 of the semiconductor integrated circuit 100. Referring to FIG. 2, power lines 201 and 202 (VDD and GND) are arranged in a lattice form, and a decoupling capacitor 204 for reducing noises of the power lines 201 and 202 is arranged within a core 203 in the same manner as FIG. 1.
Referring to FIGS. 1 and 2, the decoupling capacitors 104 and 204 are arranged in regions separated from regions where the power lines 101, 102, 201, and 202 are arranged within the semiconductor integrated circuits 100 and 200, i.e., in regions different from the regions where the power lines are arranged, so that the decoupling capacitors 104 and 204 disadvantageously occupy some regions of the cores 103 and 203. Further, when capacitances of the decoupling capacitors 104 and 204 increase, areas occupied by the decoupling capacitors 104 and 204 in the respective cores 103 and 203 increase by the increased amount of the capacitors. When the decoupling capacitors 104 and 204 are arranged, functions of the decoupling capacitors 104 and 204 are degraded due to connection line resistance from the power lines 101, 102, 201, and 202 to the decoupling capacitors 104 and 204.
To cope with the problems resulting from FIGS. 1 and 2, a parasitic capacitor formed between power lines formed of metal (i.e., a capacitor of which charge capacitance is accumulated between power lines as power is applied between the power lines) may be used. FIG. 3 illustrates a layout for increasing a parasitic capacitor between power lines in a conventional semiconductor integrated circuit (refer to U.S. Pat. No. 5,789,807 entitled “On-chip power distribution for improved decoupling”). Referring to FIG. 3, power lines 301 and 302 (VDD and GND) are cross-coupled in a semiconductor integrated circuit 300, so that a parasitic capacitor formed between the power lines can be used as a decoupling capacitor.
However, when the semiconductor integrated circuit 300 is arranged as shown in FIG. 3, capacitance of the capacitor is relatively smaller compared to the case that the decoupling capacitor is arranged in a separate region of the core as shown in FIGS. 1 and 2, so that the capacitor having a sufficient capacitance cannot be provided.